How SPI Flash Works

March 23, 2026

How SPI Flash Works

SPI Flash—specifically SPI NOR Flash—is the small, non‑volatile memory device that stores BIOS/UEFI firmware in most modern laptops. It provides fast, predictable reads and supports XIP (Execute In Place), allowing early firmware to run directly from the chip without first copying to RAM. For the complete knowledge hub, see the BIOS Guide.

1) What SPI Flash Is

SPI NOR Flash is a floating‑gate based memory connected over the Serial Peripheral Interface (SPI). It combines high data retention with low pin count packages (e.g., SOIC‑8, WSON‑8), making it ideal for motherboard firmware storage. Compared with parallel NOR, SPI NOR reduces pins and board space while keeping reliable random reads for code execution.

Before diving deeper, you may also want to review: SPI BIOS Chips Explained, BIOS Boot Process Explained, BIOS Firmware Architecture, BIOS vs UEFI: What’s the Difference?, and 3.3V vs 1.8V BIOS Chips.

2) SPI Bus Signals

A typical SPI flash uses four primary signals: SCLK (clock), MOSI (controller → flash), MISO (flash → controller), and CS# (chip select, active low). Some devices also expose WP# and HOLD# for write‑protect and bus pause. These lines let the platform controller reliably clock commands in and read data out with minimal pins.

3) Read Operation (How Code Is Fetched)

Controller asserts CS# low to select the chip.
Controller sends a READ opcode (e.g., 0x03/0x0B) plus a 24‑/32‑bit address on MOSI.
Flash decodes the command and shifts out data on MISO in sync with SCLK.
Controller samples the stream and places bytes into cache or instruction fetch buffers. With XIP‑capable mappings, the CPU can fetch directly.

4) Program (Write) Flow

Because flash cells must be erased before programming, a safe write flow looks like this:

Send WREN (Write Enable) to set the internal latch.
Issue Page Program with target address + up to 256 bytes of data.
Poll the status register’s BUSY bit until the device finishes programming.
Optionally read back and verify.

5) Erase Flow (Sector / Block)

Erase resets large regions to 0xFF in one step (commonly 4KB sectors; larger 32KB/64KB blocks exist). After erase, subsequent Page Program operations set selected bits from 1→0 to record new data.

6) Single/Dual/Quad/Octal SPI Modes

While classic SPI uses one data line in each direction, many chips support Dual/Quad/Octal modes to move multiple bits per clock. Firmware selects the highest supported mode that still meets signal integrity and controller limits during boot.

7) Why Laptops Use SPI NOR for BIOS/UEFI

Predictable latency and byte‑random reads for code execution.
High reliability and data retention suited to critical boot code.
Low pin count and compact packages simplify motherboard routing.

These traits make SPI NOR the default choice for storing platform firmware compared with parallel NOR or SPI NAND in code‑storage roles.

8) Technician Tips

Backup first: always dump the entire contents before erasing or programming.
Programmer & clip: if in‑circuit reads fail, isolate power rails or remove the chip and program off‑board.
Voltage matters: use a 1.8V adapter for low‑voltage families (e.g., “U” series) and never undervolt/overvolt.
Verify after write; poor clip contact or wrong mode causes verify errors.